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Western Digital

Chief Memory Chip Design Engineer & Architect

San Jose, CA, United States · On-site · Full time · Senior level

About the role

Lead the memory design architecture from concept to silicon qualification. Make key technical decisions and mentor engineers.

What you’ll do

• Define memory subsystem architecture and design specs. • Drive floorplan and physical architecture decisions. • Own multi-generation roadmap and scaling. • Decide cross-functional trade-offs. • Own design methodology and EDA/CAD strategy.

What you’ll bring

• MS/PhD in EE, CE or related field. • 15+ years in memory or mixed-signal IC development. • 5+ years as architect or chief engineer. • Deep CMOS FinFET expertise. • Experience with Cadence/Synopsys flows.

Life at Western Digital

Comprehensive benefits including paid leave, insurance, stock plans, tuition reimbursement, and 401(k). Inclusive and diverse culture.

About Western Digital

Western Digital builds infrastructure for the AI-driven data economy, powering hyperscale data centers and cloud platforms worldwide.

Posted 4 hours ago